| 3 | 1/1 | 返回列表 |
| 查看: 909 | 回復(fù): 2 | |||
彬彬3028木蟲 (正式寫手)
|
[求助]
UVM
|
|
怎么學(xué)好UVM 發(fā)自小木蟲Android客戶端 |

鐵蟲 (正式寫手)
鐵蟲 (職業(yè)作家)
|
RE: https://www.quora.com/What-shoul ... sVerilog-being-used UVM is written in SystemVerilog and uses OOP concepts to develop test benches for verification on FPGAs and ASICs. Knowing Verilog is a good start, but SystemVerilog is considered a HVL (High Verification Language) 不說(shuō) SV / OOP 了解多少, 讓人怎么幫你 ?? 如果 SV / OOP 你都熟, 可照下面鏈接學(xué) https://www.quora.com/What-are-s ... nd-UVM-from-scratch |
| 3 | 1/1 | 返回列表 |
| 最具人氣熱帖推薦 [查看全部] | 作者 | 回/看 | 最后發(fā)表 | |
|---|---|---|---|---|